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LTC3441 1 3441fa regulated output with input above, below or equal to the output single inductor, no schottky diodes high efficiency: up to 95% 25 a quiescent current in burst mode operation up to 1.2a continuous output current from a single lithium-ion true output disconnect in shutdown 2.4v to 5.5v input range 2.4v to 5.25v output range 1mhz fixed frequency operation synchronizable oscillator selectable burst mode or fixed frequency operation <1 a quiescent current in shutdown small, thermally enhanced 12-lead (4mm 3mm) dfn package high current micropower synchronous buck-boost dc/dc converter handheld computers handheld instruments mp3 players digital cameras burst mode is a registered trademark of linear technology corporation. efficiency vs v in the ltc 3441 is a high efficiency, fixed frequency, buck- boost dc/dc converter that operates efficiently from input voltages above, below or equal to the output voltage. the topology incorporated in the ic provides a continuous trans- fer function through all operating modes, making the prod- uct ideal for single lithium ion or multicell applications where the output voltage is within the battery voltage range. the device includes two 0.10 n-channel mosfet switches and two 0.11 p-channel switches. external schottky diodes are optional, and can be used for a moderate efficiency improvement. the operating frequency is internally set to 1mhz and can be synchronized up to 1.7mhz. quiescent current is only 25 a in burst mode operation, maximizing battery life in portable applications. burst mode operation is user controlled and can be enabled by driving the mode/sync pin high. if the mode/ sync pin is driven low or with a clock, then fixed fre- quency switching is enabled. other features include a 1 a shutdown, soft-start control, thermal shutdown and current limit. the LTC3441 is available in a thermally enhanced 12-lead (4mm 3mm) dfn package. v in (v) 2.5 50 efficiency (%) 60 70 80 3 3.5 4 4.5 3441 ta02 5 90 100 55 65 75 85 95 5.5 i out = 200ma i out = 1a v out = 3.3v sw1 pv in v in shdn/ss mode/sync pgnd 5 8 12 11 2 6 4 9 10 1 7 3 sw2 v out fb v c gnd pgnd LTC3441 c in 10 f *1 = burst mode operation 0 = fixed frequency c in : taiyo yuden jmk212bj106mg c out : taiyo yuden jmk325bj226mm l1: toko a916cy-4r7m 2.5v to 4.2v li-ion * 15k 340k c out 22 f v out 3.3v 1a 200k 1.5nf 3441 ta01 l1 4.7 h features descriptio u applicatio s u typical applicatio u li-ion to 3.3v at 1a buck-boost converter lt, ltc and ltm are registered trademarks of linear technology corporation.
LTC3441 2 3441fa v in , v out voltage ........................................ 0.3v to 6v sw1, sw2 voltage dc ........................................................... 0.3v to 6v pulsed < 100ns ...................................... 0.3v to 7v shdn/ss, mode/sync voltage ................. 0.3v to 6v operating temperature range (note 2) .. 40 c to 85 c maximum junction temperature (note 4) ........... 125 c storage temperature range ................ 65 c to 125 c order part number (note 1) absolute axi u rati gs w ww u package/order i for atio uu w consult ltc marketing for parts specified with wider operating temperature ranges. LTC3441ede t jmax = 125 c ja = 53 c/w 1-layer board ja = 43 c/w 4-layer board jc = 4.3 c/w exposed pad is pgnd (pin 13) must be soldered to pcb de part marking 3441 12 11 10 9 8 7 1 2 3 4 5 6 fb v c v in pv in v out mode/sync shdn/ss gnd pgnd sw1 sw2 pgnd top view 13 de12 package 12-lead (4mm 3mm) plastic dfn the denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v in = v out = 3.6v,unless otherwise noted. electrical characteristics parameter conditions min typ max units input start-up voltage 2.3 2.4 v output voltage adjust range 2.4 5.25 v feedback voltage 1.19 1.22 1.25 v feedback input current v fb = 1.22v 1 50 na quiescent current?urst mode operation v c = 0v, mode/sync = 3v (note 3) 25 40 a quiescent current?hdn v out = shdn = 0v, not including switch leakage 0.1 1 a quiescent current?ctive mode/sync = 0v (note 3) 520 900 a nmos switch leakage switches b and c 0.1 7 a pmos switch leakage switches a and d 0.1 10 a nmos switch on resistance switches b and c 0.10 pmos switch on resistance switches a and d 0.11 input current limit 2 3.2 a max duty cycle boost (% switch c on) 70 88 % buck (% switch a in) 100 % min duty cycle 0% frequency accuracy 0.85 1 1.15 mhz mode/sync threshold 0.4 1.4 v mode/sync input current v mode/sync = 5.5v 0.01 1 a error amp av ol 90 db error amp source current 14 a error amp sink current 300 a shdn/ss threshold when ic is enabled 0.4 1 1.4 v shdn/ss threshold when ea is at max boost duty cycle 2 2.4 v shdn/ss input current v shdn = 5.5v 0.01 1 a order options tape and reel: add #tr lead free: add #pbf lead free tape and reel: add #trpbf lead free part marking: http://www.linear.com/leadfree/
LTC3441 3 3441fa note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the LTC3441e is guaranteed to meet performance specifications from 0 c to 70 c. specifications over the ?0 c to 85 c operating temperature range are assured by design, characterization and correlation with statistical process controls. note 3: current measurements are preformed when the outputs are not switching. note 4: this ic includes overtemperature protection that is intended to protect the device during momentary overload conditions. junction temperature will exceed 125 c when overtemperature protection is active. continuous operation above the specified maximum operating junction temperature may result in device degradation or failure. electrical characteristics typical perfor a ce characteristics uw load transient response, 100ma to 1a v out 100mv/div 1a 100ma 100 s/div 3441 g01 v out ripple at 1a load v out 10mv/div ac-coupled buck v in = 4.2v buck-boost v in = 3.3v boost v in = 2.7v l = 4.7 h1 s/div 3441 g02 c out = 47 f i out = 1a v out = 3.3v switch pins in buck-boost mode sw1 2v/div v in = 3.3v 50ns/div 3441 g03 v out = 3.3v i out = 500ma sw2 2v/div sw1 2v/div v in = 4.2v 50ns/div 3441 g04 v out = 3.3v i out = 500ma sw2 2v/div switch pins entering buck-boost mode efficiency i out (ma) 30 efficiency (%) 90 100 20 10 80 50 70 60 40 0.1 10 100 1000 3441 g17 0 1 burst mode operation v in = 2.7v v in = 4.2v v in = 3.6v v out = 3.3v
LTC3441 4 3441fa typical perfor a ce characteristics uw active quiescent current temperature ( c) ?5 520 v in + v out current ( a) 540 560 580 600 ?5 5 35 65 3441 g06 95 125 620 530 550 570 590 610 630 v in = v out = 3.6v temperature ( c) ?5 feedback voltage (v) 65 1.241 3441 g07 5 ?5 95 35 125 1.236 1.231 1.226 1.221 1.216 1.211 1.206 1.201 1.196 v in = v out = 3.6v temperature ( c) ?5 10 v in + v out current ( a) 20 30 40 50 ?5 5 35 65 3441 g08 95 125 v in = v out = 3.6v feedback voltage burst mode quiescent current feedback voltage line regulation error amp source current error amp sink current temperature ( c) ?5 60 line regulation (db) 70 80 90 ?5 5 35 65 3441 g09 95 125 v in = v out = 2.4v to 5.5v temperature ( c) ?5 5 ea source current ( a) 10 15 20 ?5 5 35 65 3441 g10 95 125 v in = v out = 3.6v temperature ( c) ?5 200 ea sink current ( a) 250 300 350 400 ?5 5 35 65 3441 g11 95 125 v in = v out = 3.6v output frequency current limit temperature ( c) ?5 0.8 frequency (mhz) 0.9 1.0 1.1 1.2 ?5 5 35 65 3441 g12 95 125 v in = v out = 3.6v temperature ( c) ?5 2.8 current limit (a) 3.0 3.2 3.4 ?5 5 35 65 3441 g13 95 125 v in = v out = 3.6v switch pins before entering boost mode sw1 2v/div v in = 3v 50ns/div 3441 g05 v out = 3.3v i out = 500ma sw2 2v/div
LTC3441 5 3441fa typical perfor a ce characteristics uw pmos r ds(on) minimum start voltage temperature ( c) ?0 0.05 pmos r ds(on) ( ) 0.07 0.09 0.11 ?5 5 35 65 3441 g15 95 0.13 0.15 0.06 0.08 0.10 0.12 0.14 125 v in = v out = 3.6v switches a and d temperature ( c) ?5 2.10 minimum start voltage (v) 2.15 2.20 2.25 2.30 ?5 5 35 65 3441 g16 95 125 uu u pi fu ctio s shdn/ss (pin 1): combined soft-start and shutdown. applied voltage < 0.4v shuts down the ic. tie to >1.4v to enable the ic and >2.4v to ensure the error amp is not clamped from soft-start. an rc from the shutdown com- mand signal to this pin will provide a soft-start function by limiting the rise time of the v c pin. gnd (pin 2): signal ground for the ic. pgnd (pins 3, 6, 13 exposed pad): power ground for the internal nmos power switches sw1 (pin 4): switch pin where the internal switches a and b are connected. connect inductor from sw1 to sw2. an optional schottky diode can be connected from this sw1 to ground. minimize trace length to keep emi down. sw2 (pin 5): switch pin where the internal switches c and d are connected. an optional schottky diode can be connected from sw2 to v out (it is required where v out > 4.3v). minimize trace length to keep emi down. mode/sync (pin 7): burst mode select and oscillator synchronization. mode/sync = high: enable burst mode operation. during the period where the ic is supplying energy to the output, the inductor peak inductor current will reach 0.8a and return to zero current on each cycle. in burst mode operation the operation is variable frequency, which provides a significant efficiency improvement at light loads. the burst mode operation will continue until the pin is driven low. mode/sync = low: disable burst mode operation and maintain low noise, constant frequency operation . mode/sync = external clk : synchronization of the internal oscillator and burst mode operation disable. a clock pulse width between 100ns and 2 s and a clock frequency between 2.3mhz and 3.4mhz (twice the desired frequency) is required to synchronize the ic. f osc = f sync /2 v out (pin 8): output of the synchronous rectifier. a filter capacitor is placed from v out to gnd. a ceramic bypass capacitor is recommended as close to the v out and gnd pins as possible. pv in (pin 9): power v in supply pin. a 10 f ceramic capaci- tor is recommended as close to the pv in and pgnd pins as possible v in (pin 10): input supply pin. internal v cc for the ic. v c (pin 11): error amp output. a frequency compensation network is connected from this pin to the fb pin to compensate the loop. see the section ?ompensating the feedback loop?for guidelines. fb (pin 12): feedback pin. connect resistor divider tap here. the output voltage can be adjusted from 2.4v to 5.25v. the feedback reference voltage is typically 1.22v. nmos r ds(on) temperature ( c) ?5 0.05 nmos r ds(on) ( ) 0.07 0.09 0.11 0.13 0.15 ?5 53565 3441 g14 95 125 v in = v out = 3.6v switches b and c
LTC3441 6 3441fa block diagra w + + + + + + 9 10 pwm logic and output phasing gate drivers and anticross conduction burst mode operation control 5 s delay gnd uvlo 4a 2.4v sleep mode/sync 1 = burst mode operation 0 = fixed frequency 1mhz osc sync supply current limit sw a sw1 pv in v in v cc internal sw2 v in 2.4v to 5.5v sw d i sense amp error amp 1.22v clamp reverse current limit sw b 3.2a average current limit sw c pgnd 0.8a 7 2 1 + 4 5 pgnd 6 v out 8 fb 12 v c 11 shdn/ss shutdown r ss v in r2 c ss r1 3440 bd v out 2.4v to 5.25v pwm comparators + 1 100 g m = k thermal shutdown 2
LTC3441 7 3441fa operatio u the LTC3441 provides high efficiency, low noise power for applications such as portable instrumentation. the ltc proprietary topology allows input voltages above, below or equal to the output voltage by properly phasing the output switches. the error amp output voltage on the v c pin de- termines the output duty cycle of the switches. since the v c pin is a filtered signal, it provides rejection of frequen- cies from well below the switching frequency. the low r ds(on) , low gate charge synchronous switches provide high frequency pulse width modulation control at high efficiency. schottky diodes across the synchronous switch d and synchronous switch b are not required, but provide a lower drop during the break-before-make time (typically 15ns). the addition of the schottky diodes will improve peak efficiency by typically 1% to 2%. high efficiency is achieved at light loads when burst mode operation is entered and when the ic? quiescent current is a low 25 a. low noise fixed frequency operation oscillator the frequency of operation is factory trimmed to 1mhz. the oscillator can be synchronized with an external clock applied to the mode/sync pin. a clock frequency of twice the desired switching frequency and with a pulse width of at least 100ns is applied. the oscillator sync range is 1.15mhz to 1.7mhz (2.3mhz to 3.4mhz sync frequency). error amp the error amplifier is a voltage mode amplifier. the loop compensation components are configured around the amplifier to obtain stability of the converter. the shdn/ss pin will clamp the error amp output, v c , to provide a soft- start function. supply current limit the current limit amplifier will shut pmos switch a off once the current exceeds 4a typical. before the switch current limit, the average current limit amp (3.2a typical) will source current into the fb pin to drop the output voltage. the current amplifier delay to output is typically 50ns. reverse current limit the reverse current limit amplifier monitors the inductor current from the output through switch d. once a negative inductor current exceeds 800ma typical, the ic will shut off switch d. output switch control figure 1 shows a simplified diagram of how the four internal switches are connected to the inductor, v in , v out and gnd. figure 2 shows the regions of operation for the LTC3441 as a function of the internal control voltage, v ci . the v ci voltage is a level shifted voltage from the output of the error amp (v c pin) (see figure 5). the output switches are properly phased so the transfer between operation modes is continuous, filtered and transparent to the user. when v in approaches v out the buck/boost region is reached where the conduction time of the four switch region is typically 150ns. referring to figures 1 and 2, the various regions of operation will now be described. 4 sw1 5 sw2 pmos a nmos b 9 pv in pmos d nmos c 3441 f01 8 v out v out 75% d max boost d min boost d max buck duty cycle 0% v4 ( 2.05v) v3 ( 1.65v) boost region buck region buck/boost region v2 ( 1.55v) v1 ( 0.9v) 3441 f02 a on, b off pwm cd switches d on, c off pwm ab switches four switch pwm internal control voltage, v ci figure 1. simplified diagram of output switches figure 2. switch control vs internal control voltage, v ci
LTC3441 8 3441fa buck region (v in > v out ) switch d is always on and switch c is always off during this mode. when the internal control voltage, v ci , is above voltage v1, output a begins to switch. during the off time of switch a, synchronous switch b turns on for the remainder of the time. switches a and b will alternate similar to a typical synchronous buck regulator. as the control voltage increases, the duty cycle of switch a increases until the maximum duty cycle of the converter in buck mode reaches d max _ buck , given by: d max _ buck = 100 ?d4 sw % where d4 sw = duty cycle % of the four switch range. d4 sw = (150ns ?f) ?100 % where f = operating frequency, hz. beyond this point the ?our switch,?or buck/boost region is reached. buck/boost or four switch (v in ~ v out ) when the internal control voltage, v ci , is above voltage v2, switch pair ad remain on for duty cycle d max_buck , and the switch pair ac begins to phase in. as switch pair ac phases in, switch pair bd phases out accordingly. when the v ci voltage reaches the edge of the buck/boost range, at voltage v3, the ac switch pair completely phase out the bd pair, and the boost phase begins at duty cycle d4 sw . the input voltage, v in , where the four switch region begins is given by: v v ns f v in out = 1 150 ? ) the point at which the four switch region ends is given by: v in = v out (1 ?d) = v out (1 ?150ns ?f) v boost region (v in < v out ) switch a is always on and switch b is always off during this mode. when the internal control voltage, v ci , is above voltage v3, switch pair cd will alternately switch to provide a boosted output voltage. this operation is typical to a synchronous boost regulator. the maximum duty cycle of the converter is limited to 88% typical and is reached when v ci is above v4. burst mode operation burst mode operation is when the ic delivers energy to the output until it is regulated and then goes into a sleep mode where the outputs are off and the ic is consuming only 25 a. in this mode the output ripple has a variable frequency component that depends upon load current. during the period where the device is delivering energy to the output, the peak current will be equal to 800ma typical and the inductor current will terminate at zero current for each cycle. in this mode the typical maximum average output current is given by: i v vv a out max burst in out in () . + 02 burst mode operation is user controlled, by driving the mode/sync pin high to enable and low to disable. the peak efficiency during burst mode operation is less than the peak efficiency during fixed frequency because the part enters full-time 4-switch mode (when servicing the output) with discontinuous inductor current as illus- trated in figures 3 and 4. during burst mode operation, the control loop is nonlinear and cannot utilize the control voltage from the error amp to determine the control mode, therefore full-time 4-switch mode is required to maintain the buck/boost function. the efficiency below 1ma becomes dominated primarily by the quiescent current and not the peak efficiency. the equation is given by: efficiency burst ( bm) i load + 25 a i load where ( bm) is typically 75% during burst mode operation . operatio u
LTC3441 9 3441fa burst mode operation to fixed frequency transient response when transitioning from burst mode operation to fixed frequency, the system exhibits a transient since the modes of operation have changed. for most systems this tran- sient is acceptable, but the application may have stringent input current and/or output voltage requirements that dictate a broad-band voltage loop to minimize the tran- sient. lowering the dc gain of the loop will facilitate the task (5m from fb to v c ) at the expense of dc load regulation. type 3 compensation is also recommended to broad band the loop and roll off past the two pole response of the lc of the converter (see closing the feedback loop). operatio u soft-start the soft-start function is combined with shutdown. when the shdn/ss pin is brought above typically 1v, the ic is enabled but the ea duty cycle is clamped from the v c pin. a detailed diagram of this function is shown in figure 5. the components r ss and c ss provide a slow ramping voltage on the shdn/ss pin to provide a soft-start function. 9 pv in a 4 sw1 6 gnd 5 sw2 l + 8 v out d c 800ma i inductor 0ma 3441 f03 t1 b di dt v in l 9 pv in a 4 sw1 6 gnd 5 sw2 l ? 8 v out d c 800ma i inductor 0ma 3441 f04 t2 b di dt v out l + 12 11 v in error amp 1.22v 14 a fb r1 r2 c p1 v c v out 1 shdn/ss c ss 1v enable signal r ss soft-start clamp to pwm comparators chip enable 3441 f05 + v ci figure 3. inductor charge cycle during burst mode operation figure 4. inductor discharge cycle during burst mode operation figure 5. soft-start circuitry
LTC3441 10 3441fa component selection applicatio s i for atio wu uu handle the peak inductor current without saturating. molded chokes or chip inductors usually do not have enough core to support the peak inductor currents in the 1a to 2a region. to minimize radiated noise, use a toroid, pot core or shielded bobbin inductor. see table 1 for suggested components and table 2 for a list of component suppliers. table 1. inductor vendor information supplier phone fax web site coilcraft (847) 639-6400 (847) 639-1469 www.coilcraft.com coiltronics (561) 241-7876 (561) 241-9339 www.coiltronics.com murata usa: usa: www.murata.com (814) 237-1431 (814) 238-0490 (800) 831-9172 sumida usa: www.japanlink.com/ (847) 956-0666 (847) 956-0702 sumida japan: 81(3) 3607-5111 81(3) 3607-5144 output capacitor selection the bulk value of the capacitor is set to reduce the ripple due to charge into the capacitor each cycle. the steady state ripple due to charge is given by: %_ % %_ % () () () () () ripple boost ivv cv f ripple buck ivv cv vf out max out in min out out out max in max out out in max out = () = () 100 100 2 where c out = output filter capacitor, f the output capacitance is usually many times larger in order to handle the transient response of the converter. for a rule of thumb, the ratio of the operating frequency to the unity-gain bandwidth of the converter is the amount the output capacitance will have to increase from the above calculations in order to maintain the desired tran- sient response. the other component of ripple is due to the esr (equiva- lent series resistance) of the output capacitor. low esr capacitors should be used to minimize output voltage ripple. for surface mount applications, taiyo yuden ce- ramic capacitors, avx tps series tantalum capacitors or sanyo poscap are recommended. 12 11 10 9 8 7 1 2 3 4 5 6 fb v c v in pv in v out mode shdn/ss gnd pgnd sw1 sw2 pgnd v in v out gnd multiple vias 3441 f06 figure 6. recommended component placement. traces carrying high current are direct. trace area at fb and v c pins are kept low. lead length to battery should be kept short. v out and v in ceramic capacitors close to the ic pins inductor selection the high frequency operation of the LTC3441 allows the use of small surface mount inductors. the inductor cur- rent ripple is typically set to 20% to 40% of the maximum inductor current. for a given ripple the inductance terms are given as follows: l vvv f i ripple v h l vv v f i ripple v h in min out in min out max out out in max out out max in max > () > () () () () () () () % , % 100 100 where f = operating frequency, hz %ripple = allowable inductor current ripple, % v in(min) = minimum input voltage, v v in(max) = maximum input voltage, v v out = output voltage, v i out(max) = maximum output load current for high efficiency, choose an inductor with a high fre- quency core material, such as ferrite, to reduce core loses. the inductor should have low esr (equivalent series resistance) to reduce the i 2 r losses, and must be able to
LTC3441 11 3441fa input capacitor selection since the v in pin is the supply voltage for the ic it is recommended to place at least a 4.7 f, low esr bypass capacitor. table 2. capacitor vendor information supplier phone fax web site avx (803) 448-9411 (803) 448-1943 www.avxcorp.com sanyo (619) 661-6322 (619) 661-1055 www.sanyovideo.com taiyo yuden (408) 573-4150 (408) 573-4159 www.t-yuden.com optional schottky diodes the schottky diodes across the synchronous switches b and d are not required (v out < 4.3v), but provide a lower drop during the break-before-make time (typically 15ns) of the nmos to pmos transition, improving efficiency. use a schottky diode such as an mbrm120t3 or equiva- lent. do not use ordinary rectifier diodes, since the slow recovery times will compromise efficiency. for applica- tions with an output voltage above 4.3v, a schottky diode is required from sw2 to v out . output voltage < 2.4v the LTC3441 can operate as a buck converter with output voltages as low as 0.4v. the part is specified at 2.4v minimum to allow operation without the requirement of a schottky diode. synchronous switch d is powered from v out and the r ds(on) will increase at low output voltages, therefore a schottky diode is required from sw2 to v out to provide the conduction path to the output. output voltage > 4.3v a schottky diode from sw to v out is required for output voltages over 4.3v. the diode must be located as close to the pins as possible in order to reduce the peak voltage on sw2 due to the parasitic lead and trace inductance. input voltage > 4.5v for applications with input voltages above 4.5v which could exhibit an overload or short-circuit condition, a 2 /1nf series snubber is required between the sw1 pin and gnd. a schottky diode from sw1 to v in should also be added as close to the pins as possible. for the higher input voltages, v in bypassing becomes more critical; therefore, a ceramic bypass capacitor as close to the v in and gnd pins as possible is also required. operating frequency selection additional quiescent current due to the output switches gate charge is given by: buck: 800e ?2 ?v in ?f boost: 400e ?2 ?(v in + v out ) ?f buck/boost: f ?(1200e ?2 ?v in + 400e ?2 ?v out ) where f = switching frequency closing the feedback loop the LTC3441 incorporates voltage mode pwm control. the control to output gain varies with operation region (buck, boost, buck/boost), but is usually no greater than 15. the output filter exhibits a double pole response is given by: f lc hz filter pole out _ = 1 2 where c out is the output filter capacitor. the output filter zero is given by: f rc hz filter zero esr out _ = 1 2 where r esr is the capacitor equivalent series resistance. a troublesome feature in boost mode is the right-half plane zero (rhp), and is given by: f v ilv hz rhpz in out out = 2 2 the loop gain is typically rolled off before the rhp zero frequency. a simple type i compensation network can be incorpo- rated to stabilize the loop but at a cost of reduced band- width and slower transient response. to ensure proper phase margin, the loop requires to be crossed over a decade before the lc double pole. applicatio s i for atio wu uu
LTC3441 12 3441fa applicatio s i for atio wu uu the unity-gain frequency of the error amplifier with the type i compensation is given by: f rcp hz ug = 1 211 most applications demand an improved transient response to allow a smaller output filter capacitor. to achieve a higher bandwidth, type iii compensation is required. two zeros are required to compensate for the double-pole response. f erc hz which is extremely close to dc f rc hz f rc hz f rc hz pole p zero zp zero z pole zp 1 3 1 1 1 2 1 2 2 1 232 1 1 2 1 21 1 2 = = = figure 7. error amplifier with type i compensation figure 8. error amplifier with type iii compensation 1.22v r1 r2 3441 f07 fb 12 v c c p1 v out 11 + error amp 1.22v r1 r2 3441 f08 fb 12 v c c p1 c z1 r z v out 11 c p2 + error amp sw1 pv in v in shdn/ss mode/sync pgnd 5 8 12 11 2 6 4 9 10 1 7 3 sw2 v out fb v c gnd pgnd LTC3441 c1 10 f *1 = burst mode operation 0 = fixed frequency c1: taiyo yuden jmk212bj106mg c2: taiyo yuden jmk325bj476mm l1: toko a916cy-4r7m 2.5v to 4.2v li-ion * r3 15k 5m r1 348k 2.2k c2 47 f v out 3.3v 1a r2 200k c4 220pf 220pf 3441 f09 l1 4.7 h load transient response, 100ma to 1a v out 100mv/div 1a 100ma 100 s/div 3441 g01 figure 9. fast transient response compensation for step load or mode change
LTC3441 13 3441fa typical applicatio s u li-ion to 3.3v at 1.2a converter sw1 pv in v in shdn/ss mode/sync pgnd 5 8 12 11 2 6 4 9 10 1 7 3 sw2 v out fb v c gnd pgnd LTC3441 c1 10 f *1 = burst mode operation 0 = fixed frequency c1: taiyo yuden jmk212bj106mg c2: taiyo yuden jmk325bj226mm d1, d2: on semiconductor mbrm120lt3 l1: toko a916cy-3r3m 2.8v to 4.2v li-ion d2 * r3 15k r1 340k c2 22 f v out 3.3v 1.2a r2 200k c4 1.5nf 3441 ta03a l1 4.7 h d1 i out (ma) 0.1 40 efficiency (%) 50 60 70 80 1 10 10000 100 1000 3441 ta03b 30 20 10 0 90 100 4.2v in pwm 4.2v in burst 3.6v in pwm 2.8v in pwm efficiency
LTC3441 14 3441fa typical applicatio s u li-ion to 5v at 600ma boost converter with output disconnect efficiency sw1 pv in v in shdn/ss mode/sync pgnd 5 8 12 11 2 6 4 9 10 1 7 3 sw2 v out fb v c gnd pgnd LTC3441 c1 10 f 0.047 f *1 = burst mode operation 0 = fixed frequency c1: taiyo yuden jmk212bj106mg c2: taiyo yuden jmk325bj226mm d1: mbrm120lt3 l1: toko a916cy-4r7m 2.5v to 4.2v li-ion * r3 15k r1 619k c out 22 f v out 5v 600ma r2 200k c4 1.5nf 3441 ta04a l1 4.7 h d1 1m output current (ma) 30 efficiency (%) 90 100 20 10 80 50 70 60 40 0.1 10 100 1000 3441 ta04b 0 1 burst mode operation v in = 2.7v v in = 4.2v v in = 3.6 v
LTC3441 15 3441fa u package descriptio de/ue package 12-lead plastic dfn (4mm 3mm) (reference ltc dwg # 05-08-1695) information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 4.00 0.10 (2 sides) 3.00 0.10 (2 sides) note: 1. drawing proposed to be a variation of version (wged) in jedec package outline m0-229 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package 0.40 0.10 bottom view?xposed pad 1.70 0.10 0.75 0.05 r = 0.115 typ r = 0.05 typ 2.50 ref 1 6 12 7 pin 1 notch r = 0.20 or 0.35 45 chamfer pin 1 top mark (note 6) 0.200 ref 0.00 ?0.05 (ue12/de12) dfn 0806 rev d 2.50 ref recommended solder pad pitch and dimensions apply solder mask to areas that are not soldered 2.20 0.05 0.70 0.05 3.60 0.05 package outline 3.30 0.10 0.25 0.05 0.50 bsc 1.70 0.05 3.30 0.05 0.50 bsc 0.25 0.05
LTC3441 16 3441fa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 2003 lt 0507 rev a ?printed in usa related parts part number description comments lt 1613 550ma (i sw ) 1.4mhz high efficiency step-up dc/dc converter v in : 0.9v to 10v, v out(max) : 34v, i q : 3ma, i sd : 1 a, thinsot tm lt1615/lt1615-1 300ma/80ma (i sw ) constant off-time, high efficiency step-up v in : 1.2v to 15v, v out(max) : 34v, i q : 20 a, dc/dc converter i sd : 1 a, thinsot lt1616 500ma (i out ) 1.4mhz high efficiency step-down dc/dc converter high efficiency, v in : 3.6v to 25v, v out(min) : 1.25v, i q : 1.9ma, i sd : 1 a, thinsot ltc1776 500ma (i out ) 200khz high efficiency step-down dc/dc converter high efficiency, v in : 7.4v to 40v, v out(min) : 1.24v, i q : 3.2ma, i sd : 30 a, n8, s8 ltc1877 600ma (i out ) 550khz synchronous step-down dc/dc converter 95% efficiency, v in : 2.7v to 10v, v out(min) : 0.8v, i q : 10 a, i sd : 1 a, ms8 ltc1878 600ma (i out ) 550khz synchronous step-down dc/dc converter 95% efficiency, v in : 2.7v to 6v, v out(min) : 0.8v, i q : 10 a, i sd : 1 a, ms8 ltc1879 1.2a (i out ) 550khz synchronous step-down dc/dc converter 95% efficiency, v in : 2.7v to 10v, v out(min) : 0.8v, i q : 15 a, i sd : 1 a, tssop16 lt1930/lt1930a 1a (i sw ) 1.2mhz/2.2mhz high efficiency step-up dc/dc converter v in : 2.6v to 16v, v out(max) : 34v, i q : 5.5ma, i sd : 1 a, thinsot ltc3405/ltc3405a 300ma (i out ) 1.5mhz synchronous step-down dc/dc converter 95% efficiency, v in : 2.7v to 6v, v out(min) : 0.8v, i q : 20 a, i sd : 1 a, thinsot ltc3406/ltc3406b 600ma (i out ) 1.5mhz synchronous step-down dc/dc converter 95% efficiency, v in : 2.5v to 5.5v, v out(min) : 0.6v, i q : 20 a, i sd : 1 a, thinsot ltc3407 600ma (i out ) 2 1.5mhz dual synchronous step-down 96% efficiency, v in : 2.5v to 5.5v, v out(min) : 0.6v, i q : 40 a, dc/dc converter i sd : 1 a, 10-lead ms ltc3411 1.25a (i out ) 4mhz synchronous step-down dc/dc converter 95% efficiency, v in : 2.5v to 5.5v, v out(min) : 0.8v, i q : 60 a, i sd : 1 a, 10-lead ms ltc3412 2.5a (i out ) 4mhz synchronous step-down dc/dc converter 95% efficiency, v in : 2.5v to 5.5v, v out(min) : 0.8v, i q : 60 a, i sd : 1 a, tssop16e ltc3440 600ma (i out ) 2mhz synchronous buck-boost dc/dc converter 95% efficiency, v in : 2.5v to 5.5v, v out(min) : 2.5v, i q : 25 a, i sd : 1 a, 10-lead ms thinsot is a trademark of linear technology corporation. typical applicatio u sw1 pv in v in shdn/ss mode/sync pgnd 5 8 12 11 2 6 4 9 10 1 7 3 sw2 v out fb v c gnd pgnd LTC3441 c1 10 f c1: taiyo yuden jmk212bj106mg c2: sanyo mv-ax series l1: toko a916cy-4r7m v in 2.5v to 5.5v 1a max r6 24k r4 1k average input current control 1n914 r s 0.05 r1 392k c out 2200 f v out 3.6v 2a (pulsed) r2 200k r5 24k c4 10nf 3441 ta05 l1 10 h + 1/2 lt1490a 1.22 ?r4 r5 ?r s i currentlimit = 2n3906 + 1/2 lt1490a pcmcia powered gsm modem

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